Let us begin by introducing a semi systolic multiplier, so named because its design involves broadcasting a single bit of the multiplier x to a number of circuit element, thus violating the “short, local wires” requirement of pure systolic design. But as you can see this is NOT written like software.
Bit-serial multipliers can be designed as systolic arrays: synchronous arrays of processing element that are interconnected by only short, local wires thus allowing very high clock rates. I haven't shown any code for shift or for determining you've shifted 16-bits of data and now have your parallel output.
Furthermore, in applications that call for a large number of independent multiplications, multiple bit-serial multiplier may be more cost- effective than a complex highly pipelined unit. In such a case, using a parallel multiplier would be quite wasteful, since the parallelism may not lead to any speed benefit. The SN74ALS166 shown above is the closest match of an actual part to the previous parallel-in/ serial out shifter figures.
In addition, in certain application contexts inputs are supplied bit-serially anyway. SN74ALS165 parallel-in/ serial-out 8-bit shift register, asynchronous load CD4014B parallel-in/ serial-out 8-bit shift register, synchronous load SN74LS647 parallel-in/ serial-out 16-bit shift register, synchronous load.
Let assume the parallel data bus of the Parallel to Serial converter to be N bit. Parallel to Serial converter VHDL code example. In fact,the compactness of the design may allow us to run a bit- serial multiplier at a clock rate high enough to make the unit almost competitive with much more complex designs with regard to speed. If you need to transfer 16-bit data 1MHz the serial data stream speed shall be at least greater than 16 x 1 MHz 16 MHz.